- FPGA prototype
orphan date June 2010 Unreferenced date March 2009 FPGA prototyping , sometimes also referred to as ASIC prototyping or System on a chip SoC prototyping is the method to prototype SoC and ASIC design on FPGA for hardware verification and validation verification and early software development. Verification methods for hardware design as well as early software and firmware co design have become mainstream. Prototyping SoC and ASIC design on FPGA has become a good method to do this. Reason why Prototyping is important Running an SoC design on FPGA prototype is a reliable way to ensure that it is functionally correct. This is compared to designers only relying on software simulations to verify that their hardware design is sound. Simulation speed and modeling accuracy limitations hinder See also FPGA Prototype External links http www.s2cinc.com S2cinc Official Site DEFAULTSORT Fpga Prototype Category Gate arrays ... more details
|
- File:WillWare Usb fpga sch.png
Summary I Will Ware created this schematic using the Eagle PCB design software from Cadsoft. This design is for a board with a 68013 processor 8051 core with USB interface and a Xilinx FPGA. I place both the design and this image in the public domain. I have not posted the image on the web. Licensing PD self date October 2006 ... more details
|
- File:WillWare Usb fpga layout.png
Summary I Will Ware created this PCB layout using the Eagle PCB design software from Cadsoft. This design is for a board with a 68013 processor 8051 core with USB interface and a Xilinx FPGA. I place both the design and this image in the public domain. I have not posted the image on the web. Licensing PD self date October 2006 ... more details
|
- CompactRIO
not come with the modules needed to program the cRIO. The Realtime Module and FPGA modules have to be purchased ... more details
|
- Field Upgradeable Systems Environment
Orphan date February 2009 A Field Upgradeable Systems Environment FUSE is a reconfigurable computing reconfigurable computer operating system which provides a consistent and easy to use high level Interface computer science interface to FPGA based reconfigurable computing products. http www.nallatech.com Nallatech originally developed http www.nallatech.com ?node id 1.2.2&id 17 FUSE and now licence it out or supply it with FPGA hardware. Category Proprietary operating systems operating system stub ... more details
|
- Impulse C
of FPGA based applications. Impulse C is compatible with standard ANSI C , allowing standard ... accepts a subset of C and generates FPGA hardware in the form of Hardware description language ... programmers to target FPGA devices for C language application acceleration. Impulse C is distinct from standard C in that it provides a parallel programming model for mixed processor and FPGA platforms ... include standard processors along with programmable FPGA hardware. The Impulse C tools include ... technology used to map application elements to hardware via FPGA logic synthesis tools. Programming ... that is partitioned into hardware and software components, or implemented entirely within an FPGA .... On the software side of the application, for example in an embedded FPGA processor, Impulse ..., send status messages or poll for results. For processor to FPGA communications, stream reads and writes can be specified as operations that take advantage of FPGA specific, internal or external ... HDL files. These files are processed by FPGA tools to create FPGA hardware bitmaps. At the heart ... platforms Impulse C supports common FPGA based processing platforms including the Altera Nios II ... more details
|
- File:Altera CYCLONE II FPGA.jpg
Summary Information Description Altera Cyclone II FPGA Source I Reubentg created this work entirely by myself. Date April 1, 2010 Author Reubentg Personal website http students.washington.edu rtg2 other versions Licensing PD self date April 2010 ... more details
|
- File:Mm1 rc1 parts on pcb.png
Summary Information Description Prototype board of the Milkymist One interactive VJ station, including a FPGA to implement a custom open source hardware system on chip design. Source http www.milkymist.org mmone.html Date 12 03, 13 August 2010 UTC Author Adam Wang Licensing cc by sa 3.0 ... more details
|
- Structured ASIC platform
orphan date September 2008 Structured ASIC is an intermediate technology between ASIC and FPGA , offering high performance, a characteristic of ASIC, and low Non recurring engineering NRE cost, a characteristic of FPGA. Using Structured ASIC allows products to be introduced quickly to market, to have lower cost and to be designed with ease. In a FPGA, interconnects and logic blocks are programmable after fabrication, offering high flexibility of design and ease of debugging in prototyping. However, the capability of FPGAs to implement large circuits is limited, in both size and speed, due to complexity in programmable routing, and significant space occupied by programming elements, e.g. SRAMs, MUXes. On the other hand, ASIC design flow is expensive. Every different design needs a complete different set of masks. The Structured ASIC is a solution between these two. It has basically the same structure as a FPGA, but being mask programmable instead of field programmable, by configuring one or several via layers between metal layers. Every SRAM configuration bit can be replaced by a choice of putting a via or not between metal contacts. A number of commercial vendors have introduced structured ASIC products. They have a wide range of configurability, from a single via layer to 6 metal and 6 via layers. Altera s Hardcopy II, eASIC s Nextreme are examples of commercial structured ASICs. References Altera Corp HardCopy II Structured ASICs eASIC Corp Nextreme Structured ASIC Chun Hok Ho et al. Floating Point FPGA Architecture and Modelling Chun Hok Ho et al. DOMAIN SPECIFIC HYBRID FPGA ... Embedded FPGA Fabric Steve Wilton et al. A Synthesizable Datapath Oriented Embedded FPGA Fabric for Silicon ... Rose Design, Layout and Verification of an FPGA using Automated Tools Ian Kuon, Russell Tessier and Jonathan Rose FPGA Architecture Survey and Challenges Ian Kuon and Jonathan Rose Measuring the Gap ... Khye Chai A Highly Compatible Architecture Design for Optimum FPGA to Structured ASIC Migration ... more details
|
- Impulse Accelerated Technologies
Impulse Accelerated Technologies, Inc. is a privately held company providing software development tools for embedded systems and high performance computing , particularly for applications based on FPGA field programmable gate array FPGA devices. The company was formed in 2002 and is based in Kirkland, Washington . Key product is the High level synthesis tool CoDeveloper for the programming language Impulse C also developed by Impulse Accelerated Technologies. External links http www.ImpulseAccelerated.com Impulse Accelerated Technologies website Category Software companies of the United States Category Electronic design automation companies Category Companies based in Washington state Ict company stub ... more details
|
- DIME-C
Citations missing date July 2010 DIME C is a C to HDL tool developed by Nallatech it is part of their DIMEtalk Design Tools suite. It includes an editor, a compiler and a parallelization visualizer. It supports the majority of ANSI C. It generates VHDL. External links http www.nallatech.com Nallatech http www.nallatech.com index.php FPGA Development Tools dimetalk.html DIMEtalk page on Nallatech s website. http www.cse.clrc.ac.uk disco publications FPGA overview 2.0.pdf Daresbury Labs Overview an overview of flows by Daresbury Labs, includes DIME C. Category Gate arrays Category Electronic design automation software programming software stub ... more details
|
- Sopc builder
Orphan date February 2009 SOPC Builder System on a Programmable Chip Builder is software made by Altera that automates connecting soft hardware components to create a complete computer system that runs on any of its various Field programmable gate array FPGA chips. SOPC Builder incorporates a library of pre made components including the flagship Nios II soft processor , memory controller s, interfaces, and peripherals and an interface for incorporating custom ones. Interconnections are made though the Avalon bus . Bus arbitration, bus width matching, and even clock domain crossing are all handled automatically when SOPC Builder generates the system. A GUI is the only thing used to configure the soft hardware components which often have many options and to specify the bus topology . The resulting virtual system can then be connected to the outside world via the FPGA s programmable pins or connected internally to other soft compoments. The FPGA s pins are routed to connectors, such as for PCI or DDR, or as is often the case in embedded systems to other chips mounted on the same PCB. Resource utilization on an FPGA hosting an SOPC Builder system is very modest by modern standards. FPGA devices supporting SOPC systems include almost all Altera FPGAs and even some CPLDs ranging from 5 to 5,000 in price. See also System on a chip SoC System on a chip SoPC SoPC System on Programmable Chip Field programmable gate array FPGA Field programmable gate array reconfigurable computing Soft microprocessor Category Gate arrays ru SOPC Builder ... more details
|
- Glossary of reconfigurable computing
Refers to total on chip memory available for multi FPGA systems. Auto sequencing memory ASM Anti machine ... at run time. Bitstream The file that configures the FPGA has a .bit extension . The Bitstream gets loaded into an FPGA when ready for execution. Obtained after place and route, final result of the place and route phase. Common Memory A.k.a Shared Memory. Should refer to memory on a multi FPGA board to which all the FPGAs can communicate data to DIRECTLY and is external to the FPGA. Compile Compilation ... loaded on an FPGA. When used loosely, it could also refer to the components chipset making up ... that exactly mimics the clock on the FPGA, records changes in data based on the rising falling edge ... of an ASIC design on FPGA based hardware or a processor based system or in the case of simulation ... HPC FPGA s or Reconfigurable Data Path Array rDPA s characterized by large run times and computing ... should been used purely to describe memory that is external to an FPGA or Reconfigurable Data Path Array rDPA , is attached directly to an FPGA, and is not attached to any other FPGA or device ... chip with the FPGA or Reconfigurable Data Path Array rDPA . Morphware Another term for Reconfigurable ... mapped and placed components on the FPGA or Reconfigurable Data Path Array rDPA , ending in the creation ... pairs a comventional microprocessor host computer with a reconfigurable co processor, such as an FPGA .... Newer FPGA based architectures eliminate the need for a host processor by providing mechanisms to configure ... devices as co processors. Newer FPGA based architectures eliminate the need for a host processor by providing ... and network interfaces, the device drivers, and so forth. Current FPGA devices allow partial ... in system on chip design. Reconfigurable Device FPGA s, Reconfigurable Data Path Array rDPA s, and any ... may have a fine grained architecture like FPGA s, or a coarse grained architecture like Reconfigurable ... more details
|
- Partial re-configuration
. Typically the design modules are built along well defined boundaries inside the FPGA that require the design ... of the device while the rest of an FPGA is still running static partial reconfiguration the device is not active during the reconfiguration process. While the partial data is sent into the FPGA, the rest .... There are two styles of partial reconfiguration of FPGA devices from Xilinx module based and difference ... reconfiguration of an FPGA. Difference based partial reconfiguration can be used when a small change ... design structure that resides in the FPGA and the new content of an FPGA. There are two ways ... of the FPGA. References Reflist External links External links date August 2010 Resources ... PUB.FILE&FILE ID 231 Measurement of Reconfiguration Delay in a System with a Xilinx Virtex FPGA It appears ... more details
|
- FpgaC
C for execution as FPGA circuits has become a main stream technology. Commercial FPGA C compilers are available ... description and simulation languages. FPGA based Reconfigurable Computing offerings from industry ... xc pdf p006 008 58 execview.pdf FPGA System Level Tools Category C compilers Category Programming language ... more details
|
- SiliconBlue Technologies
first Kevin authorlink coauthors title SiliconBlue Debuts Low Power FPGAs work FPGA and Structured ... pdf 20080603 newkid.pdf format doi accessdate 2009 03 25 ref ref name FPGA cite web last Maxfield first Clive authorlink coauthors title The first new FPGA fabric in the last 10 years? work Programmable ... advance in FPGA design and will potentially open up new markets to FPGAs where they had not been ... The SiliconBlue iCE65 FPGA family is manufacted by TSMC using 65 nm process ref name TSMC ... ref . The iCE65 FPGAs can be configured similar to other RAM based FPGAs. Optionally, the FPGA can load its configuration from internal Nonvolatile Configuration Memory NVCM . SiliconBlue s FPGA fabric .... Configuration Like other RAM based FPGA, SiliconBlue mobileFPGAs are configured immediately after ... SPI Flash, SPI Slave, with configuration data downloaded to the mobile FPGA by external microcontroller ... JTAG , which is available only on certain package options SiliconBlue iCE65 Ultra Low Power FPGA ... last Clark first Peter authorlink coauthors title FPGA startup aims at the handset work EETimes publisher ... images can be selected coldboot mode , or then at run time reconfiguration can be invoked from the FPGA ... FPGA and Structured ASIC Journal publisher Techfocus Media, Inc. date July 3, 2008 url http www.fpgajournal.com ... fpga SBT FPGA Google group DEFAULTSORT Siliconblue Technologies Category Electronics companies of the United ... more details
|
- Bitstream
dablink For other uses of this term, see Bitstream disambiguation . unreferenced date June 2007 A bitstream or bit stream is a time series of bit s. A bytestream is a series of byte s, typically of 8 bits each, and can be regarded as a special case of a bitstream. Bitstreams are used extensively in telecommunications and computing for example, the Synchronous Digital Hierarchy SDH communications technology transports synchronous bitstreams, and the Transmission Control Protocol TCP communications protocol transports a bytestream without synchronous timing. When a bitstream is captured and stored in a computer storage medium, a computer file is created. The term bitstream is frequently used to describe the configuration data to be loaded into a field programmable gate array FPGA . This usage may have originated based on the common method of configuring the FPGA from a serial bit stream, typically from a serial programmable read only memory PROM or flash memory chip, although most FPGAs also support a byte parallel loading method as well. The detailed format of the bitstream for a particular FPGA chip is usually considered proprietary to the FPGA vendor. In mathematics, several specific sequence mathematics infinite sequences of bits have been studied for their mathematical properties these include the Baum Sweet sequence , Ehrenfeucht Mycielski sequence , Fibonacci word , Kolakoski sequence , regular paperfolding sequence , Rudin Shapiro sequence , and Thue Morse sequence . See also Elementary stream MPEG Elementary stream Bitstream format Bit stream access Category Binary sequences Category Data transmission Category Reconfigurable computing de Bitstrom ko hu Bitstream pt Fluxo de bits ru th zh ... more details
|
- Critical Path
Critical Path may refer to Critical path method , an algorithm for scheduling of activities Time for one logical block within an FPGA to propagate a signal www.edn.com file 1081 CTLRCNIut 6983 0508.pdf?force true Critical Path book by Buckminster Fuller Critical Path video game , an interactive movie computer game The Critical Path by Northrop Frye 1971 disambig th ... more details
|
- Nios embedded processor
for School level education board in India National Institute of Open Schooling Nios was Altera s first configurable 16 bit embedded processor for its FPGA product line. For new designs, Altera recommends the 32 bit Nios II . It is now considered obsolete. Citation needed date November 2009 Soft microprocessors DEFAULTSORT Nios Embedded Processor Category Soft microprocessors Microcompu stub de Nios fr NIOS ... more details
|
- Soft microprocessor
one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a multi core processor . The number of soft processors on a single FPGA is only limited by the size of the FPGA. ref http www.xilinx.com products design resources proc central microblaze ... or hundreds of soft microprocessors on a single FPGA. ref Istv n Vass nyi. Implementing processor arrays ... HAMMAMI. A 24 Processors System on Chip FPGA Design with Network on Chip . http www.design reuse.com ... ADOH Processor based FPGA Design Embedded Design on Altium Wiki http wiki.altium.com display ADOH ... based FPGA Design Embedded Design on Altium Wiki OpenSPARC OpenSPARC T1 Sun Microsystems Sun yes ... or 32 bit. Supports ASIC and FPGA. http www.ensilica.com ip esi risc.htm EnSilica eSi RISC LatticeMico32 ... computer bus Wishbone 32 bit Done in ASIC, Actel, Altera, Xilinx FPGA http opencores.org project,or1k ... programmable gate array FPGA Field programmable gate array reconfigurable computing References Reflist ... library digital soft cpu cores Soft CPU Cores for FPGA http ews.uiuc.edu pdabrows soft processor comparison.html Detailed Comparison of 12 Soft Microprocessors broken link? http www.fpgacpu.org FPGA CPU ... more details
|
- Erasable programmable logic device
Unreferenced date December 2009 Orphan date October 2006 EPLD stands for Erasable programmable logic device and is an integrated circuit that comprises an array of programmable logic devices that do not come pre connected the connections are programmed electrically by the user. See also CPLD Macrocell array Programmable array logic PAL Programmable logic device PLD Field programmable gate array FPGA DEFAULTSORT Erasable Programmable Logic Device Category Gate arrays de Erasable Programmable Logic Device ... more details
|
- Virtex
Virtex is a series of FPGA s produced by Xilinx Virtex family Xilinx . Virtex is a series of comic books published by Oktomica Comics . Virtex L otherwise known as Sodium dithionite . VirTex is a virgin TeX disambig Short pages monitor This long comment was added to the page to prevent it being listed on Special Shortpages. It and the accompanying monitoring template were generated via Template Longcomment. Please do not remove the monitor template without removing the comment as well. ... more details
|
- FPLA
FPLA may refer to Fair Packaging and Labeling Act a United States law that applies to labels on many consumer products Field programmable logic array a type of semiconductor device better known as field programmable gate array FPGA Popular Liberation Front of Azawad in French Front Populaire de Lib ration de l Azawad a militant rebel group in northern Mali Free piston linear alternator essentially a linear motor used as an electrical generator disambig de FPLA ... more details
|
- T80
T80 or T 80 may refer to T 80 tank , a Soviet Union main battle tank Canon T80 , a 1985 35mm SLR camera Mercedes Benz T80 , a vehicle designed to break the world land speed record Route T80, a T Way bus service operated by Western Sydney Buses and also T 80 light tank, a variant of the WWII Soviet T 70 tank an open source version of Zilog Z80 FPGA and ASIC versions Zilog Z80 computer processor disambig hr T 80 razdvojba ... more details
|
- PipeRench
The PipeRench Reconfigurable Computing Project is a project from the Carnegie Mellon University intended to improve reconfigurable computing systems. It aims to allow Hardware assisted virtualization hardware virtualization through high speed reconfiguration, in order to minimize resource constraints in FPGA s and similar systems. The project has already succeeded in manufacturing a chip and testing it. PipeRench has been licensed by a start up Rapport http www.rapportincorporated.com and is the basis of their KiloCore chip. External links http www.ece.cmu.edu piperench PipeRench official site Category Reconfigurable computing ... more details
|
Encyclopedia
top
